1. Field of the Invention
This invention relates to dynamic random access memories (DRAMs) and, more particularly, to an improved technique for refreshing DRAM memory cells.
2. Prior Art
Data is stored in a DRAM memory storage cell using charge that is stored on a capacitor in each memory storage cell. The presence or absence of stored charge represents either a one or a zero bit in a memory cell. The stored charge leaks away through various leakage mechanisms, and over time, the data represented by the charge is lost unless the charge stored in the memory storage cell is periodically refreshed with a refresh circuit to restore the charge. Because of this leakage, a refresh operation is typically required every 64 milliseconds. The need for a periodic refresh operation affects both external interface functions and control functions of the DRAM. DRAMs are constructed such that whenever a row of a DRAM is addressed, the memory storage cells in that row are automatically refreshed, regardless of whether the row addressing is for a READ, A WRITE, or a REFRESH operation.
The timing signals for an asynchronous DRAM are not synchronized to a system clock. An asynchronous DRAM is provided with an external row address select (RAS) command signal and with an external column address select (CAS) signal. During normal operation of an asynchronous DRAM, a RAS signal occurs before a CAS signal. In order to perform a typical refresh operation in an asynchronous DRAM, a CAS signal occurs before a RAS signal.
The timing signals for a synchronous DRAM are synchronized to a system clock so that timing is better controlled and the DRAM can operate at higher speeds. In an synchronous DRAM, an address strobe signal is generated when an address signal level transition is detected in one or more address signal lines. The first part of the address is a row address and the second part of the address is a column address that is provided after one or more clock pulses. RAS and CAS signals are generated in a synchronous DRAM and used with an auto-refresh command to refresh the charge in the memory cells.
Alternatively, many types of conventional asynchronous and synchronous DRAMs are refreshed by being placed in a standby mode with an external command. In the standby mode, a memory cell refresh is performed internally and this type of refreshing is referred to as a xe2x80x9cself refresh.xe2x80x9d
Various prior art schemes have been disclosed for hiding an internal refresh operation in a DRAM. These types of prior art schemes generally add more complexity to a DRAM to obtain higher speeds and better performance, whereas low power and reductions of circuit complexity and circuit area are usually desired for a DRAM.
One such prior art scheme is disclosed in a U.S. Pat. No. 5,999,474, granted to Leung et al. The ""474 apparatus uses an SRAM cache and an associated cache tag memory, where the SRAM cache has a storage capacity that is {fraction (1/64)}th of the storage capacity of the DRAM. The SRAM cache has two separate very wide 256-bit read and write data buses. One disadvantage of the disclosed ""474 apparatus is the large amount of circuit area is required by the SRAM cache. Since SRAM cache cells typically use 9 to 10 times the area of a DRAM memory cell, the additional area required for ""474 apparatus is close to 15% of the area used for the DRAM memory arrays. Another disadvantage of the disclosed ""474 apparatus is the need for the two separate wide data buses that are used to write and to read a cache line. This makes power consumption for the disclosed ""474 apparatus dependent on the cache hit profile, which can result in high peak power and in high sustained power for certain situations.
Another prior art scheme is disclosed in a U.S. Pat. No. 5,596,545, granted to Lin for a semiconductor device with internal self-refreshing. The ""545 apparatus uses a comparator to detect when there is a conflict between a refresh operation and a write operation. The comparator consumes silicon area and power unnecessarily and provides no performance advantage.
Another such prior art scheme is disclosed in a U.S. Pat. No. 5,835,401, granted to Green et. al. that describes a circuit for hiding a refresh operation of DRAM cells in a memory device. The ""401 apparatus uses a shift register to speed up the generation of the refresh address. The ""401 apparatus also requires either an external CLK signal or an external CE* signal to control the refresh operation. The disadvantages of the ""401 apparatus are the increased silicon area required for the shift register and the need for an external CLK or CE signal to initiate the refresh operation.
FIG. 1 illustrates a generic DRAM system 10 that is shown to illustrate refreshing of either an asynchronous DRAM or a synchronous DRAM. The generic DRAM system 10 includes a DRAM memory cell array, or block, 12 that is arranged as rows and columns of memory cells. While a single DRAM array 12 is shown, it is understood that in a conventional DRAM there are typically several arrays of DRAM memory cells and these arrays are arranged as a set of several banks of memory cells. Individual rows of the DRAM array 12 are selected with a corresponding wordline, or row select, signal that is provided on one of a plurality of wordlines that are provided in a wordline bus 14. The wordline signals are provided from a decoder/wordline driver circuit 16 that is activated by a decoder control signal on a control line 18. Multi-bit address signals are inputted on a multi-line bus 20 to the decoder/wordline driver circuit 16 from a two-input multiplexer circuit 22. The two-input multiplexer circuit 22 selects external address signals from a multi-line memory address bus 24 or internal address signals on a multi-line bus 26 from a multi-bit refresh counter 28. Selection of the output of the multiplexer 22 is controlled by a multiplexer control signal that is provided on a control line 30.
The DRAM array 12 is enabled with an array enable signal that is provided on a signal line 32. A sense amplifier/read-write circuit 34 for data in and out of the DRAM array 12 is controlled by a memory read-write control signal on a control line 36. For reading out data stored in one of the memory cells in the array 12, the sense amplifier is used to detect the charge level in that memory cells to provide an output data bit on an I/O bus 38. For writing data into one of the memory cells, input data is read into the memory cells of the array 12 from the I/O bus 38.
A RAS control and memory timing circuit 40 provides the decoder control signal on control line 18. The RAS control and memory timing circuit 40 provides the array enable signal on the signal line 32. The RAS control and memory timing circuit 40 also provides the memory read-write control signal on the control line 36.
For both asynchronous and synchronous types of DRAMS, an external RAS signal is provided at a RAS input terminal 42. The RAS input terminal 42 is connected to an input terminal of a refresh command decode circuit 44 and is also connected to one input terminal of a two-input multiplexer 46. For normal memory-access operations of the memory array 12, that is, for read or write operations, the RAS signal is passed through the two-input multiplexer 46 to a signal line 48 that is connected to an input terminal of the RAS control and memory timing circuit 40. This RAS signal produces appropriate control signals on control line 18, 32, and 36, as previously mentioned.
For an asynchronous DRAM, an external CAS signal is provided at a CAS input terminal 50 of the refresh command decode circuit 44. For a synchronous DRAM, an external AUTO REFRESH signal is also provided at an AUTO REFRESH input terminal 52 of the refresh command decode circuit 44. During a normal memory-access operation of an asynchronous DRAM, a RAS signal is presented to input terminal 42 before a CAS signal is presented to CAS input terminal 50. To initiate a refresh operation in a typical asynchronous DRAM the sequence of RAS and CAS signals is reversed so that a CAS signal is presented to CAS input terminal 50 before a RAS signal is presented to RAS input terminal 42. This CAS-before-RAS refresh sequence is detected by the refresh command decode circuit 44 to produce a refresh RFSH output signal on an output signal line 54 of the refresh command decode circuit 44.
For a synchronous DRAM, a refresh operation is initiated when an AUTO REFRESH command signal is received at input terminal 52 of the refresh command decode circuit 44 to produce a refresh RFSH output signal on signal line 54. The RFSH signal on line 54 activates a refresh enable circuit 56. The activated refresh enable control circuit 56 provides three output signals as follows: An oscillator enable signal is provided on a signal line 60 to turn on a self refresh oscillator circuit 62. An output signal from the self-refresh oscillator 62 is provided on a signal line 64 to one input terminal of a two-input OR gate 66 that has its output terminal connected with a signal line 68 to an input terminal of the refresh counter 28. The refresh counter 28 keeps track of the memory word line that is being refreshed in the self-refresh mode. The refresh enable control circuit 56 also provides a pulse on a signal line 70 at the end of a refresh cycle to another input terminal of the two-input OR gate 66 in order to increment the refresh counter 28 to the address of the next wordline to be refreshed in the self-refresh mode of operation. The refresh enable control circuit 56 also provides the multiplexer control signal on the control line 30 to select the internal address signals that are provided on the multi-bit bus 26 from the multi-bit refresh counter 28. The multiplexer control signal on the control line 30 is also connected to a control terminal of the two-input multiplexer 46 to provide a self-refresh equivalent RAS signal from the refresh enable control circuit 56 on signal line 48 to the RAS control and timing circuit 40.
It is evident from the operation of the system of FIG. 1 that conventional refresh schemes for both asynchronous and synchronous DRAMS require that external input signals need to be provided and need to be properly decoded prior to initiation of a refresh cycle.
For refreshing an asynchronous DRAM with external RAS and CAS signals, a CAS-before-RAS signal sequence must be decoded by the refresh command decode circuit 54. For refreshing a synchronous DRAM, an external AUTO REFRESH signal needs to be decoded. In both case external signals and signal sequences are required to initiate an internal memory refresh sequence.
For many DRAM applications, it would be advantageous to have a simplified interface and control scheme to provide refreshing for the memory cells without the use of additional external control signals. It would also be advantageous that the circuitry for controlling and for performing DRAM refresh operations be as simple as possible and require a minimum of such circuitry. It would also be advantageous that a DRAM memory be organized so that the refresh function consumes minimal power and is executed within a prescribed period of time. Metastability in decision circuits can cause problems when nearly simultaneous request signal are received. Loss of a non-selected request is also a problem.
Consequently, a need exists for a DRAM device that has a simple external interface that requires no external refresh commands or input signal sequences and that does not lose non-selected refresh or external-access requests. It is desirable that minimal circuitry and minimal power are needed to perform a refresh operations of a DRAM.
The present invention provides a DRAM with a simple external interface that eliminates the need for any additional external control signal to initiate a refresh operation for the DRAM. The present invention provides a DRAM with reduced power dissipation by a DRAM during a refresh operation by providing that the DRAM is broken into smaller DRAM blocks, or arrays, with fewer memory cells in each DRAM block so that less power is used for each refresh cycle. The present invention reduces the power dissipated by a DRAM when it is in a standby mode when only refresh cycles are being executed by the DRAM. The refresh technique according to the invention internally schedules refresh cycles for completion within a predetermined period of time while performing arbitrary write or read access cycles. The refresh technique according to the invention also internally schedules write or read cycles for completion within a predetermined period of time while performing refresh cycles. For multiple DRAM blocks, scheduling of refresh cycles and/or write or read access cycles uses an arbitration and selection circuit.
One embodiment of a DRAM system according to the invention includes a plurality of DRAM cell blocks, or arrays, with each DRAM block having an associated counter or other refresh address generating means and where only one such counter or address generating means is active during a given refresh cycle.
The present invention provides a memory device which includes one or more DRAM memory cell arrays and a control circuit for accessing and refreshing the DRAM memory cells. The control circuit is coupled to an internal oscillator and executes refresh cycles at times independently determined by the oscillator. The one or more DRAM memory cell arrays are structured so that a row access operation, whether for write, or read, or refresh, consumes relatively little power and may be performed in a relatively short time. This results in the external interface for the DRAM being very simple, similar to that of an SRAM because no external signals are required for control of a refresh operation. The oscillator frequency is set by design to provide a refresh request signal at predetermined intervals as required by the leakage characteristics of the DRAM cells. This refresh request signal is asynchronous with respect to a row access command that may occur in response to an external write or read access command. The control circuit receives row access commands and refresh requests and schedules corresponding operations as these commands occur. If a refresh operation is in progress and a row access command is initiated, the row access operation is delayed until the refresh operation is completed. If a row access operation is in progress and a refresh request occurs, the refresh is delayed until the row access is completed. If both a row access and a refresh occur effectively simultaneously, the row access operation is given priority and the refresh operation is scheduled to begin upon completion of the row access operation.
Each refresh counter has associated with it an enable flip-flop which serves both to enable the local counting and to enable refresh of the associated array. Thus, only one counter is incremented at any given time and only one memory array is refreshed in response to a refresh request. The enable flip-flops are so connected that once a given counter completes its count, a subsequent enable flip-flop is set to thereby enable a subsequent counter. The enable flip-flop for the current counter is cleared to thereby prevent the current counter from further counting until its enable flip-flop is next set.
Although a DRAM is preferably organized as several DRAM blocks, or arrays, to reduce the amount of switching activity and hence the power dissipation, the control circuit may also be coupled to only one memory array or several control circuits may be used, where each control circuit is coupled to its associated set of memory arrays.
One embodiment of the present invention provides a DRAM system with internal refreshing of memory cells. This embodiment is for a single DRAM array of memory cells arranged in word rows where each word row has a row access line for receiving a row line select signal that refreshes DRAM memory cells in the word row. A wordline decoder receives multi-bit row-line address signals and provides row-line select signals to corresponding row access signal lines. A wordline address multiplexer receives a mux control signal to provide internally-provided refresh wordline input address signals to the wordline decoder; the wordline address multiplexer otherwise provides externally-provided row-line address signals to the wordline decoder. A self refresh internal oscillator circuit provides an internal self-refresh RFSH output signal. A row-access-select RAS input terminal receives a row access select RAS input signal for the DRAM array. An arbitration and selection circuit receives the RFSH signal and an input RAS signal and provides a refresh selection SEL_RFSH command output signal to initiate an internal memory-cell refresh cycle when the RFSH input signal is selected and given priority by the arbitration and selection circuit. The arbitration and selection circuit provides a RAS selection SEL_RAS command output signal to initiate a read or write memory-cell cycle when the RAS input signal is selected and given priority by the arbitration and selection circuit. A memory array timing circuit is activated by the SEL_RFSH signal or the RAS signal to provide enable signals for the DRAM array and the wordline decoder. The memory array timing circuit also providing the mux control signal to the wordline address multiplexer to select the internal refresh counter internal wordline address signals. A refresh counter is incremented by the SEL_RFSH signal and provides the internal refresh counter internal wordline address signals REF_ADDR signals to the wordline address multiplexer. Internal refreshing of the DRAM memory cells requires no additional external control signals for internally refreshing the DRAM array. The DRAM system of this embodiment may also include DRAM arrays of DRAM memory cells where each array has an associated refresh counter and where only one such associated refresh counter is active during a given refresh cycle for the DRAM system.
The arbitration and selection circuit internally schedules refresh cycles for completion within a predetermined period of time while performing arbitrary write or read access cycles. The arbitration and selection circuit internally schedules write or read cycles for completion within a predetermined period of time while performing refresh cycles.
Another embodiment of the invention includes two or more DRAM blocks of memory cells, where each DRAM block is arranged in word rows and each of said word rows has a row access signal line for receiving a row-access select signal that causes DRAM memory cells in a corresponding word row to be addressed and refreshed. This DRAM system has a self-refresh internal oscillator circuit that provides an internal self-refresh (RFSH) output signal for the DRAM system. A RAS input terminal receives an input row access select (RAS) signals for the DRAM system. An arbitration and selection circuit that receives the RFSH signal and the input RAS signal and that arbitrates between those two signals to provide two alternative output signals: one of which is an internal-refresh selection SEL_RFSH command output signal when the RFSH input signal is given priority by the arbitration and selection circuit and the other of which is an external-address selection SEL_RAS command output signal when the RAS input signal is given priority by the arbitration and selection circuit. Each DRAM block has a corresponding wordline decoder that receives multi-bit row-line address input signals and that also receives a wordline-decoder control signal to provide row-access select output signals to corresponding row access signal lines. Each DRAM block has a corresponding wordline address multiplexer that provides either internally-provided refresh wordline input address signals REF_ADDR to the wordline decoder or externally-provided row-line address signals to the wordline decoder. Each DRAM block has a refresh counter subsystem that includes a refresh counter that is selected to provide internal refresh address signals and that includes a counter-enable latch circuit for holding a token status signal, wherein the counter-enable latch circuits for all of the DRAM blocks are serially connected together for serial passing of the token status signal a corresponding adjacent counter-enable latch circuits and wherein a refresh counter that has the token status signal is enabled to be sequentially incremented by a series of SEL_RFSH signals to sequentially provide the internal refresh counter internal wordline address REF_ADDR signals to a corresponding wordline address multiplexer. Each refresh counter has associated with it an enable flip-flop which serves both to enable the local counting and to enable refresh of the associated array such that only one counter is incremented at any given time and only one memory array is refreshed in response to a refresh request. Each DRAM block has a local block control circuit that is selectively activated in either an internally generated refresh mode or in an external-address mode, both of which modes provide control signals for selecting and enabling a corresponding DRAM block and for initiating a timing chain for the corresponding DRAM block. The external-address mode is activated by both the SEL_RAS signal and an external address signal for a corresponding DRAM array; and the internally generated refresh mode is activated by the SEL_RFSH signal for a refresh counter whose counter-enable latch circuit holds the token status signal Internal refreshing of the DRAM blocks of memory cells according to the present invention requires no additional external signals for internally refreshing the DRAM blocks.
For the DRAM system with two or more DRAM arrays, the associated enable flip-flops are so connected such that once a given counter completes its count, a subsequent enable flip-flop is set to thereby a subsequent counter and such that the enable flip-flop for the current counter is cleared to thereby prevent the current counter from further counting until its enable flip-flop is subsequently set. Each refresh counter subsystem includes a detector circuit that detects that the refresh counter has reached a predetermined count and that generates a control signal which passes a token status signal to an adjacent refresh counter-enable latch circuit to enable that adjacent refresh counter. Each local block control circuit generates a finish pulse that is fed to the arbitration and control circuit to generate another SEL_RFSH signal or a SEL_RAS signal for a RFSH signal or a RAS signal that was not previously given priority. The self-refresh internal oscillator circuit provides a periodic internal self-refresh (RFSH) output signal for the DRAM system at a frequency that provides refreshing of the DRAM memory cells as required by the leakage characteristics of the DRAM memory cells. The arbitration and selection circuit provides that: if a refresh operation is in progress and a row access RAS command is initiated, the row access operation is delayed until the refresh operation is completed; if a row access operation is in progress and a refresh request occurs, the refresh is delayed until the row access is completed; and if both a row access and a refresh occur effectively simultaneously, the row access operation is given priority and the refresh operation is scheduled to begin upon completion of the row access operation. The refresh request signal RFSH is asynchronous with respect to a row access RAS command that occur in response to an external write or read access command. The arbitration and selection circuit receives the RFSH signal and the input RAS signal and arbitrates between those two signals to provide two output signals: one of which is an internal-refresh selection SEL_RFSH command output signal when the RFSH input signal is given priority by the arbitration and selection circuit and the other of which is an external-address selection SEL_RAS command output signal when the RAS input signal is given priority by the arbitration and selection circuit.
A method is provided according to the present invention for internally refreshing memory cells of a DRAM array. The method includes receiving a row line select signal that refreshes DRAM memory cells in the word row of the DRAM array; receiving a multi-bit row-line address at a wordline decoder that provides row-line select signals to corresponding row access signal lines of the DRAM array; providing internally-provided refresh wordline input address signals to the wordline decoder through a wordline address multiplexer that receives a mux control signal, said wordline address multiplexer otherwise providing externally-provided row-line address signals to the wordline decoder; providing an internal self-refresh RFSH output signal with a self refresh internal oscillator circuit; receiving a row access select RAS input signal for the DRAM array; receiving the RFSH signal and an input RAS signal with an arbitration and selection circuit that provides a refresh selection SEL_RFSH command output signal to initiate an internal memory-cell refresh cycle when the RFSH input signal is selected and given priority by the arbitration and selection circuit and that provides a RAS selection SEL_RAS command output signal to initiate a read or write memory-cell cycle when the RAS input signal is selected and given priority by the arbitration and selection circuit; activating a memory array timing circuit that is activated by the SEL_RFSH signal or the RAS signal to provide enable signals for the DRAM array and the wordline decoder, said memory array timing circuit also providing the mux control signal to the wordline address multiplexer to select the internal refresh counter internal wordline address signals; and incrementing a refresh counter that is incremented by the SEL_RFSH signal and that provides the internal refresh counter internal wordline address signals REF_ADDR signals to the wordline address multiplexer; whereby internal refreshing of the DRAM memory cells requires no additional external control signals for internally refreshing the DRAM array.
The method includes providing a plurality of arrays of DRAM memory cells where each array has an associated refresh counter and where only one such associated refresh counter is active during a given refresh cycle for the DRAM system.
An arbitration and control system is provided for a DRAM memory device that has a SRAM interface. This system includes control circuitry for self refresh operations. An address transition detector includes an address stable timer that provides a delayed control signal that allows arbitration latch metastability to be resolved. A refresh latch is provided to hold a refresh request and an external access latch is provided to hold a pending external RAS cycle request. The control system starts either an refresh cycle or an external RAS cycle first and, after the termination of that cycle, executes the other cycle. Timers are provided to properly tailor the durations of the refresh and external RAS access signals to the characteristics of a particular DRAM type.
An arbitration and control system for a self-refresh DRAM includes an address transition detection (atd) block, a refresh control block, and an external-access RAS control block. The address transition detection block receives an address transition signal a_in and provides an addr_stable output signal to indicate that an address transition has occurred and that a new address is stable. A refresh control block is provided that receives a refresh request signal ref_req signal, the addr_stable signal, and a row-address-select xras_time1_b signal and that provides a ref_time_b output signal that initiates an internal refresh of a DRAM row. A RAS control block is provided that receives the addr_stable signal and the ref_time_b signal and that provides a row-address-select xras_time1_b output signal which selects a DRAM row for a read or write operation. The refresh control block also includes an arbitration latch that arbitrates between the ref_req signal and the addr_stable signal. The arbitration latch is set in response to the ref_req signal to provide the ref_time1_b output signal. The arbitration latch is reset by the addr_stable signal.
A metastable condition of the arbitration circuit, that is caused by close arrival of the ref_req signal and the addr_stable signal, is resolved with the transition detector block including a delay circuit that delays the effect of the addr_stable signal until a metastable condition in the arbitration circuit is resolved. The address transition detection block does not provide an output signal unless a write-enable we or a chip enable ce signal is received by the address transition detection block.
An idle control block provides an output signal when the xras_time1_b signal is inactive and provides no output signal when the addr_stable signal is active to thereby inhibit the ref_time_b output signal and to prevent initiation of an internal refresh of a DRAM row. A 35 input AND function receives an output signal from the arbitration latch, the output signal from the idle control block 726, and the xras_time1_b signal such that the output signal of the 3-input AND function triggers a timer circuit that provides the ref_time_b signal.
The refresh control block includes a flip-flop circuit that is set by the ref_req signal and reset by the ref_time_b output signal to hold a refresh request. A refresh timer circuit provides a predetermined active pulse width to the ref_time1_b signal to properly time the refresh access duration. The RAS control block includes a RAS flip-flop circuit that is set by the addr_stable signal and that is reset by the xras_time1_b signal to hold an external RAS cycle request and wherein the RAS flip-flop circuit has an output signal that is gated through a two-input AND gate with an inactive ref_time_b signal. A RAS timer circuit provides a predetermined active pulse width to the sras_time1_b signal to properly time the duration of an external access to the DRAM memory device.